1. Field of the Invention
The present invention generally relates to programmable chip systems. More specifically, the invention relates to mechanisms and techniques for booting FPGA-based embedded systems.
2. Description of Related Art
The central processing unit (CPU) of an embedded system must start up or “boot” when it first receives power and then again whenever it receives a reset pulse. Usually, the instructions that the processor executes are stored in nonvolatile memory (e.g., EPROM, EEPROM, or ROM) or in a nonvolatile memory on the micro-controller device.
In embedded systems that contain a field programmable gate array (FPGA), the FPGA must configure itself when it first receives power and then again whenever it receives a reconfigure pulse. Usually, the configuration data for an FPGA is also stored in a separate nonvolatile memory.
Although storing the CPU instructions and the FPGA configuration data on separate nonvolatile memories is typical for most FPGA-based embedded systems, storing them together on a single nonvolatile parallel configuration memory may suffice as well.
To further elaborate on the above, one approach has an external nonvolatile memory that contains FPGA configuration data, and the configured FPGA contains a boot ROM in its design. In this case, the data for the FPGA's ROM is stored as part of the FPGA configuration and is loaded into the FPGA's RAM, which then acts like a boot ROM. The CPU just needs to boot normally by accessing instructions in the boot ROM. The disadvantage of this approach is that it uses relatively expensive on-chip RAM to hold the CPU instructions.
Another approach has an external nonvolatile parallel memory that contains both FPGA configuration data and CPU boot instructions written to non-overlapping locations. A CPU that is part of the configured FPGA retrieves instructions directly from the external nonvolatile parallel memory. This approach has the advantage that no on-chip RAM is needed for boot memory, but it has the disadvantage that accessing external nonvolatile memory is slow.
Another approach instructs the CPU to copy the boot instructions to external SRAM or SDRAM to enhance the performance of the executing system. The CPU then transfers execution to the copy of the boot code in SRAM or SDRAM. These kinds of memory are much less expensive than on-chip RAM and faster than off-chip nonvolatile memory, but they have many address and data pins which must be connected to corresponding FPGA pins, thereby adding to the FPGA cost.
Yet another approach has an external configuration controller that configures the FPGA with data from an external nonvolatile parallel memory. The disadvantage of this approach is that it uses an additional external logic device.
Therefore, it is desirable to provide improved methods and apparatus for booting FPGA-based embedded systems in order to better utilize FPGA resources, improve system performance, and/or minimize associated costs.